
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity ADC_accell is
    Port ( 
		clk_in		: in  STD_LOGIC;	-- input clk, twice frequency of output clock	
		eoc			: in  STD_LOGIC;	-- end of conversion, will be sent out as oe
		clk_out		: inout STD_LOGIC;  -- clock out, half of input frequency
		oe				: out std_logic;  -- output enable
		start			: out STD_LOGIC;  -- start signal, will be timed to be eoc
		addrA			: inout STD_LOGIC;  -- address A input, will toggle between potentiometers
		ale			: out STD_LOGIC	-- address latch enable, toggled high when correct address is sent		
	 );
end ADC_accell;

architecture Behavioral of ADC_accell is
	signal C_S		: integer:=1; -- current state
	signal N_S		: integer:=0; -- next state
begin
	Clock:
	process(clk_in)
	begin
		if rising_edge(clk_in) then
			C_S <= N_S;
			clk_out <= not clk_out;
		end if;
	end process;
	States:
	process (C_S, addrA, eoc)
	begin
		if (C_S = 1) then
			addrA <= not addrA; -- input selected
			N_S <= 2;
		elsif (C_S = 2) then
			ale <='1';
			N_S <= 3;
		elsif (C_S = 3) then
			ale <='1';
			start <='1';
			N_S <= 4;
		elsif (C_S = 4) then
			ale <='0';
			start <='1';
			N_S <= 5;
		elsif (C_S = 5) then			
			start <='0';
			N_S <= 6;
		elsif (C_S = 6) then
			if (eoc = '1') then
				oe <= '1';
				N_S <= 7;
			end if;
		elsif (C_S = 7) then
			N_S <= 8;
		elsif (C_S = 8) then
			N_S <= 9;
		elsif (C_S = 9) then
			N_S <= 10;
		elsif (C_S = 10) then
			oe <= '0';
			N_S <= 1;			
		end if;		
	end process;

end Behavioral;